In the typical manufacture of lightly-doped drain (LDD) transistors, a first layer of polysilicon is etched to form a gate, and source and drain regions are lightly doped using the gate as a mask. Then sidewall spacers are formed by forming oxide on the sides of the polysilicon gate. The sidewall spacers act as a mask for a subsequent heavy implant so that a portion of each of the source and drain regions is heavily doped. One of the main purposes of using LDD transistors is to reduce the number of hot electrons which are generated. In LDD structures, however, the generation of hot electrons can be an even bigger problem than in structures which have a heavily-doped drain immediately adjacent to the channel. The hot electrons which are generated by impact ionization get into the oxide immediately above the lightly-doped regions of the LDD structures and modulate the series resistance which reduces the transconductance of the transistor. One solution to this problem has been disclosed in an article, "A New LDD Transistor With Inverse T-Gate Structure," Tial-Yuan Huang et al, IEEE Electron Device Letter, Vol. EDL-8, No. 4, Apr. 1987. In that case the structure involved an inverse T-shaped polysilicon gate which had a thick portion over the channel and a thin portion which was implanted through by the first implant to form the lightly-doped portions of the source and drain. Sidewall spacers were formed on the thick portion of the polysilicon gate for the mask for the second, heavy implant.
The inverse-T structure, however, has been difficult to reproduce. Thus, the advantages of the structure have been difficult to commercialize because of the absence of a process which could reliably reproduce the inverse-T structure. One of the proposed methods is to stop etching polysilicon when the polysilicon becomes sufficiently thin. This has not been effective as a manufacturing process because of the difficulty of controlling etch rates with the required precision. The etch rate varies even over a single wafer. Thus wafer-to-wafer variation and lot-to-lot variation of polysilicon etch rates has not been considered feasible to control to the degree necessary.
Another problem in LDD structures has been the difficulty in removing sidewall spacers without causing adverse effects. There are situations, however, in which it is desirable to remove the sidewall spacers. One such example is integrated circuits which have an on-board memory array of floating gate transistors. In such situations, the floating gate transistors which comprise the array use hot electrons to advantage so that the LDD structure is undesirable for these transistors which comprise the array, whereas it is desirable for the peripheral circuits to have LDD transistors. In order to make the floating gate transistors non-LDD it is necessary to remove the sidewall spacers prior to a heavy source/drain implant.